PIC18F4539T-I/ML【PDF 70/322 页】IC MCU FLASH 12KX16 EE A/D 44QFN

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2002 Microchip Technology Inc.

Preliminary

DS30485A-page 159

PIC18FXX39

16.4.14

SLEEP OPERATION

While in SLEEP mode, the I2C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor

from SLEEP (if the MSSP interrupt is enabled).

16.4.15

EFFECT OF A RESET

A RESET disables the MSSP module and terminates

the current transfer.

16.4.16

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions allows the

determination of when the bus is free. The STOP (P)

and START (S) bits are cleared from a RESET, or when

the MSSP module is disabled. Control of the I2C bus

may be taken when the P bit (SSPSTAT<4>) is set, or

the bus is IDLE, with both the S and P bits clear. When

the bus is busy, enabling the SSP interrupt will generate

the interrupt when the STOP condition occurs.

In multi-master operation, the SDA line must be moni-

tored for arbitration, to see if the signal level is the

expected output level. This check is performed in

hardware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

Address Transfer

Data Transfer

A START Condition

A Repeated START Condition

An Acknowledge Condition

16.4.17

MULTI -MASTER COMMUNICATION,

BUS COLLISION, AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a '1' on SDA, by letting SDA float high and

another master asserts a '0'. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a '1' and the data sampled on the SDA pin = '0',

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag BCLIF and reset the I2C

port to its IDLE state (Figure 16-25).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are de-asserted, and

the SSPBUF can be written to. When the user services

the bus collision Interrupt Service Routine, and if the

I2C bus is free, the user can resume communication by

asserting a START condition.

If a START, Repeated START, STOP, or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are de-asserted, and the respective control bits in

the SSPCON2 register are cleared. When the user ser-

vices the bus collision Interrupt Service Routine, and if

the I2C bus is free, the user can resume communication

by asserting a START condition.

The master will continue to monitor the SDA and SCL

pins. If a STOP condition occurs, the SSPIF bit will be set.

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of START and STOP conditions allows the

determination of when the bus is free. Control of the I2C

bus can be taken when the P bit is set in the SSPSTAT

cleared.

FIGURE 16-25:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data doesn’t match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCLIF)

by the master.

by master

Data changes

while SCL = 0

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